1. Field of the Invention
The invention relates generally to data transfers between circuits operating in different clock domains and more specifically relates to rapid capture of flow control errors in exchange of data through a FIFO between a source producing circuit and a consuming circuit operable in different clock domains.
2. Discussion of Related Art
Data transfers between a data producing circuit and a data consuming circuit often use a FIFO (first in first out memory buffer) to compensate for speed differences when the producer and consumer circuits operate in different clock domains—i.e., different clock frequencies. For example, a serial attached SCSI (SAS) core logic circuit may be coupled to a host system bus (e.g., a PCI bus) for exchange of information between a SAS device and the host system. The SAS core logic is often coupled to the host system bus control logic using a FIFO because the signaling speeds relating to SAS data exchanges and that of the host system bus exchanges are often different—i.e., they each operate in associated but different clock domains.
The FIFO serves to buffer data from the producing circuit at its normal operating speed in its clock domain such that the consuming circuit may retrieve and process the data at its normal operating speed in its separate and different clock domain. In such a circuit some flow control is typically required. Simple flow control logic such as signals indicating when the FIFO is empty, full, or above/below and intermediate threshold capacity serves to hold off the producer if the consumer is slower at consuming the data produced and stored in the FIFO. However, if the producing circuit erroneously places too little or too much information in the FIFO for a particular exchange then the simple flow control is inadequate to detect the error. Similarly, if the consuming circuit erroneously retrieves too much or too little data for a particular exchange, the simple flow control logic is inadequate to detect such an error. These errors may be referred to herein as “over-run” and “under-run” errors or conditions. Such an error may not be detected until much later after many more exchanges have been attempted between the producer and consumer. At such later time, higher layer control logic may detect unexpected sequences of information and flag an error condition. However, the underlying cause, i.e., the error by the consumer or the producer, is far removed from the later detection of an erroneous exchange. This problem raises significant challenges in design and test of a circuit including such a producer/consumer exchange.
Thus it is an ongoing challenge to improve the timing for detecting such an error in a FIFO exchange of information between a producing circuit and a consuming circuit each operable in different clock domains.